1. Field of the Invention
The present invention relates to a processor resetting method, more particularly to a processor resetting method and apparatus for resetting a processor within such an Asynchronous Transfer Mode (which will be referred to merely as ATM, hereinafter) node as an ATM switching system, a multiplexer, or a terminal through a channel.
2. Description of the Related Art
A Broadband aspects of Integrated Services Digital Network (which will be referred to merely as B-ISDN, hereinafter) comprises ATM nodes such as ATM switching systems, multiplexers, or terminals and lines for interconnection between the ATM nodes.
Each of the ATM nodes generally includes at least one processor which communicates with another processor within the same node or a processor within another node. In such inter-processor communication, processor resetting can be realized when the sender processor transmits a resetting instruction to the receiver processor and the receiver processor executes the received instruction.
This type of prior art is known, for example, as a technique standardized by CCITT (Comite Consultatif International des Telegraphique et Telephonique, International Telegraph and Telephone Consultative Committee) X.25. When it is desired to reset one terminal belonging to an X.25 network from another terminal therein, the sender terminal transmits a packet indicative of reset instructions to the receiver terminal. The receiver terminal identifies the received packet and executes its reset processing. The format of the reset instruction packet is previously standardized.
The above prior art, however, has had a problem that, when it is desired to reset one of the processors within one terminal, it is necessary for the processor to identify a reset instruction frame, so that, when the processor is in a runaway condition or the like, the processor cannot accept the reset instruction and thus cannot be reset.